A typical switching element for a communication network has an interface including one or more input ports and a buffer for receiving and temporarily storing incoming data cells, an interface including one or more output ports, for transmitting the incoming data cells onto the next appropriate links of the communication network and a controller for controlling the transfer of data cells between the interfaces. The input buffer may include a number of queues for storing different data cells depending on, for example, the sources of the data cells, the type of data cells and the type of service associated with the data cells. For example, the input buffer may include a number of groups of queues in which different groups store data cells according to different priority of service levels. The controller includes a scheduler, which is responsible for determining the order of queues from which data cells are transferred to the output interface for transmission onto the network. A scheduler including its decision making functionality is implemented in hardware, for example, on an application specific integrated circuit (ASIC).
Various methods have been proposed to test the performance of a packet scheduler, either when implemented as a software model, before synthesis to silicon, or when implemented in hardware.
An example of a system for assessing the performance of a hardware implemented packet scheduler is described in U.S. Pat. No. 6,173,325 (Kukreja), issued on Jan. 9, 2001. In the technique disclosed in this document, a computer system is connected to an Ethernet network and arranged to capture all packets originating at various nodes of the network for a specified period of time. During capture, trigger packets are periodically inserted into the stream of captured packets, and the captured and trigger packets are stored in a file for analysis. The contents of the file are successively transferred to an analyser which includes a dynamic link library (DLL) for measuring the scheduler performance. Analysis is performed on each data packet between successive trigger packets using appropriate software modules. The trigger packets are used to identify those packets transmitted on the network in a particular quantum of time to assist in determining packet rates and bandwidth calculations. The analyser calculates the statistics for the detected network traffic from which the performance of the scheduler is determined.
To assist in the design of integrated circuits, computer aided design and simulation systems have been developed which model aspects of the structure and functionality of the circuit for testing. While basic circuit components such as a basic random access memory can be modelled relatively simply, complex structures, for example, comprising a combination of logic and memory components are more difficult to model. U.S. Pat. No. 6,080,203 (Njinda et al.) issued on Jun. 27, 2000, describes a method of modelling more complex circuitry, such as a register file for an Ethernet network switch, which includes integral memory and logic portions. The register file is modelled by partitioning the logic and memory portions to simplify the logical structure of the register file, so that the now simplified memory model and logic models can be tested separately using existing design tools such as an Automatic Test Pattern Generation (ATPG) system. The accuracy of the model is then verified by actual gate level implementation. If the outputs of the model and actual gate implementation match, the accuracy of the model is verified and the model stored for future use.
In testing the performance of a simulated circuit, a stimulus, for example, a test signal is applied to the input of the model and the response of the model is monitored and verified by monitoring output signals from the device. In the case of simulating a packet scheduler circuit, the performance of the scheduler is tested and verified by generating and supplying test cells to the scheduler and comparing the test cells output from the scheduler with the test cells predicted to be output from the scheduler, based on knowledge and the timing of the test cells supplied to the scheduler and the functional description of the scheduler circuit model, which may include details of the timing of various internal operations. However, such a monitor is difficult and time consuming to implement due to the necessary level of knowledge required for operation of the monitor concerning the timing of internal tasks performed by the scheduler.